DSP56307 Features

High-performance DSP56300 core	- 100 Million Instructions Per Second (MIPS) with a 100 MHz clock at 2.5 or 3.3V.
	- Object code compatible with the DSP56000 core
	- Highly parallel instruction set
	- Fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC)
	- 56-bit parallel barrel shifter
	- 24-bit or 16-bit arithmetic support under software control
	- Position independent code support
	- Addressing modes optimized for DSP applications
	- On-chip instruction cache controller
	- On-chip memory-expandable hardware stack
	- Nested hardware DO loops
	- Fast auto-return interrupts
	- On-chip concurrent six-channel DMA controller
	- On-chip Phase Lock Loop (PLL) and clock generator
	- On-Chip Emulation (OnCETM) module
	- JTAG Test Access Port (TAP)
	- Address Tracing mode reflects internal accesses at the external port

Memory

On-chip memories	- 64K on-chip RAM total
	- Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable
	- 192 x 24-bit bootstrap ROM

Memory Expansion Possibilities

Off-chip memory expansion	- Data memory expansion to two 256 K x 24-bit word memory spaces
	- Program memory expansion to one 256 K x 24-bit word memory space
	- External memory expansion port
	- Chip Select Logic for glueless interface to SRAMs
	- On-chip DRAM Controller for glueless interface to DRAMs

Peripherals

On-chip peripherals	- 3.0 through 3.6 V I/O interface
	- General-purpose, fully programmable Enhanced Filter Coprocessor (EFCOP) performs filtering tasks concurrently with the DSP core with minimum core overhead
	- 8-bit parallel Host Interface (HI08) supports a variety of buses (e.g., industry-standard architecture) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
	- Two Enhanced Synchronous Serial Interfaces (ESSI)
	- Serial Communications Interface (SCI) with baud rate generator
	- Triple timer module
	- Up to 34 programmable General-Purpose I/O pins (GPIO), depending on which peripherals are enabled

Power Consumption

Reduced power dissipation	- Very low-power CMOS design
	- Wait and Stop low-power standby modes
	- Fully-static logic, operation frequency down to DC
	- Optimized power management circuitry